1. Field of the Invention
The present invention relates generally to semiconductors and, more particularly, to a method for compensating for process variations in the manufacturing of semiconductor devices.
2. Description of Related Art
Integrated circuit memory technology continues to evolve toward smaller and smaller geometries. While reductions in channel-lengths and gate-oxide thicknesses in metal-oxide-semiconductor (MOS—, e.g., PMOS, NMOS, CMOS) memories can be used to improve memory performance relative to, for example, read/write speeds, such design changes often lead to increased sensitivity to manufacturing process variations and to greater sensitivity to variations in external supply voltage and temperature.
Data in integrated circuit memories must be read out in relatively short times. Read speed is critical in applications such as mobile phones and digital versatile disk (DVD) players. In order to be acceptable for use in these contexts, a need exists in the prior art for reliably controlling read-speed timing of integrated circuit memories within predetermined ranges. Further, a need exists for maintaining the read speeds within the predetermined ranges, even in the presence of variations in external supply voltage, temperature and process variations, any of which may be introduced into an environment of mass semiconductor device production.